Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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01/08/2008
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Application #:
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10269414
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Filing Dt:
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10/11/2002
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Inventors:
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Harish Devanagondi, Nicholas Bambos, Harish Belur, Richard Heaton, Majid Torabi
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Title:
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QUEUEING ARCHITECTURE AND LOAD BALANCING FOR PARALLEL PACKET PROCESSING IN COMMUNICATION NETWORKS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3260 JAY STREET |
| SANTA CLARA, CALIFORNIA 95054 |
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| FENWICK & WEST LLP |
| EILEEN A. LEHMANN, ESQ. |
| TWO PALO ALTO SQUARE |
| PALO ALTO, CA 94306 |
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Assignment:
2
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CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
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| 170 WEST TASMAN DRIVE |
| SAN JOSE, CALIFORNIA 95134-1706 |
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| KAREN HALLOCK, CISCO SYSTEMS, INC. |
| 170 WEST TASMAN DRIVE |
| SJC/10/2/1 |
| SAN JOSE, CA 95134-1706 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 170 WEST TASMAN DRIVE |
| SAN JOSE, CALIFORNIA 95134-1706 |
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| KAREN HALLOCK, CISCO SYSTEMS, INC. |
| 170 WEST TASMAN DRIVE |
| SJC/10/2/1 |
| SAN JOSE, CA 95134-1706 |
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