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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
02/19/2008
Application #:
10377884
Filing Dt:
03/04/2003
Publication #:
Pub Dt:
01/15/2004
Inventors:
Sumio Matsuda, Satoshi Kuboyama, Yasushi Deguchi
Title:
INVERTER, SEMICONDUCTOR LOGIC CIRCUIT, STATIC RANDOM ACCESS MEMORY AND DATA LATCH CIRCUIT
Assignment: 1
Reel/Frame:
020266/0349Recorded: 12/19/2007Pages: 6
Conveyance:
CHANGE OF NAME (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
12/13/2002
Assignee:
44-1, JINDAIJI HIGASHI-MACHI 7-CHOME
CHOFU-SHI, TOKYO, JAPAN
Correspondent:
JACOBSON HOLMAN PLLC
400 SEVENTH STREET, NW
WASHINGTON, DC 20004
Assignment: 2
Reel/Frame:
013843/0524Recorded: 03/04/2003Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
02/27/2003
Exec Dt:
02/27/2003
Exec Dt:
02/27/2003
Assignee:
WORLD TRADE CENTER BUILDING 2-4-1, HAMAMATSU-CHO, MINATO-KU
TOKYO, JAPAN 105-8060
Correspondent:
JACOBSON HOLMAN PLLC
ALLEN S. MELSER
400 SEVENTH STREET, NW
WASHINGTON, DC 20004

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