Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/29/2008
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Application #:
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11108741
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Filing Dt:
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04/19/2005
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Publication #:
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Pub Dt:
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10/27/2005
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Inventors:
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Hiroki Ishida, Takashi Nishimura
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Title:
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FALSE LOCK DETECTION CIRCUIT AND FALSE LOCK DETECTION METHOD, PLL CIRCUIT AND CLOCK DATA RECOVERY METHOD, COMMUNICATION DEVICE AND COMMUNICATION METHOD, AND OPTICAL DISK REPRODUCING DEVICE AND OPTICAL DISK REPRODUCING METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-35 KITASHINAGAWA 6-CHOME |
| SHINAGAWA-KU |
| TOKYO 141-0001, JAPAN |
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| RONALD P. KANANEN |
| RADER, FISHMAN & GRAUER PLLC |
| 1233 20TH STREET, N.W. |
| SUITE 501 |
| WASHINGTON, DC 20036 |
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