Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/12/2010
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Application #:
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10042512
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Filing Dt:
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10/18/2001
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Publication #:
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Pub Dt:
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06/19/2003
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Inventors:
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Pawan Kulshreshtha, Robert J. Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
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Title:
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TRANSISTOR-LEVEL TIMING ANALYSIS USING EMBEDDED SIMULATION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE |
| SAN JOSE, CALIFORNIA 94134 |
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| MICHAEL A. GLENN |
| 3475 EDISON WAY, SUITE L |
| MENLO PARK, CA 94025 |
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