Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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01/26/2010
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Application #:
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11397945
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Filing Dt:
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04/04/2006
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Publication #:
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Pub Dt:
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11/16/2006
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Inventors:
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Jean-Philippe Cousin, Jean-Jose Berenguer, Gilles Pelissier
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Title:
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CACHE COHERENCY IN A SHARED-MEMORY MULTIPROCESSOR SYSTEM
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 29 BOULEVARD ROMAIIN ROLLAND |
| FR-92120 MONTROUGE, FRANCE |
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| DOCKET CLERK |
| P.O. DRAWER 800889 |
| DALLAS, TEXAS 75380 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| WTC SCHIPHOL AIRPORT |
| SCHIPHOL BOULEVARD 265 |
| AMSTERDAM, NETHERLANDS 1118 BH |
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| STMICROELECTRONICS, INC. |
| 750 CANYON DRIVE, SUITE 300 |
| COPPELL, TX 75019 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 47 RUE DE LA VICTOIRE |
| PARIS, FRANCE |
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| BAKER & HOSTETLER LLP |
| WASHINGTON SQUARE, SUITE 1100 |
| 1050 CONNECTICUT AVENUE, N.W. |
| WASHINGTON, DC 20036 |
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Assignment:
4
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2091, GYEONGCHUNG-DAERO, BUBAL-EUB, ICHEON-SI |
| GYEONGGI-DO, KOREA, REPUBLIC OF |
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| IP & T GROUP LLP |
| 8230 LEESBURG PIKE |
| SUITE 650 |
| VIENNA, VA 22182 |
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