Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/16/2010
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Application #:
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12039742
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Filing Dt:
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02/29/2008
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Publication #:
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Pub Dt:
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04/23/2009
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Inventor:
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Shun-Ker Wu
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Title:
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TEST SYSTEM AND METHOD FOR REDUCING TEST SIGNAL LOSS FOR INTEGRATED CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| HWA-YA TECHNOLOGY PARK 669, FUHSING 3 RD., KUEISHAN |
| TAO-YUAN HSIEN, TAIWAN |
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| WINSTON HSU |
| P.O.BOX 506 |
| MERRIFIELD, VA 22116 |
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