Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/24/2014
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Application #:
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13094796
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Filing Dt:
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04/26/2011
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Publication #:
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Pub Dt:
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11/01/2012
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Inventors:
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Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
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Title:
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MEMORY DEVICE HAVING BURIED BIT LINE AND VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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HWA-YA TECHNOLOGY PARK 669, FUHSING 3 RD., KUEISHAN |
TAO-YUAN HSIEN, TAIWAN |
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WINSTON HSU |
P.O.BOX 506 |
MERRIFIELD, VA 22116 |
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