Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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01/20/2015
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Application #:
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13411515
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Filing Dt:
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03/02/2012
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Publication #:
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Pub Dt:
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09/06/2012
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Inventors:
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Lawrence S. PELLACH, Edward H. TRUEX, Bhupen SHAH
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Title:
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STAGGERED POWER-UP AND SYNCHRONIZED RESET FOR A LARGE ASIC OR FPGA
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| THREE CLOCK TOWER PLACE |
| SUITE 100 |
| MAYNARD, MASSACHUSETTS 01754 |
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| WOLF, GREENFIELD & SACKS, P.C. |
| 600 ATLANTIC AVENUE |
| BOSTON, MA 02210 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 170 WEST TASMAN DRIVE |
| SAN JOSE, CALIFORNIA 95134 |
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| RHONDA ZAFFINO |
| CISCO TECHNOLOGY INC. |
| 3 MILL AND MAIN PLACE, SUITE 400 |
| MAYNARD, MA 01754 |
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