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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
09/08/2015
Application #:
14391161
Filing Dt:
10/07/2014
Publication #:
Pub Dt:
04/09/2015
Inventor:
Stefan Poledna
Title:
Method and Master Clock for Generating Fail-Silent Synchronization Messages
Assignment: 1
Reel/Frame:
033906/0508Recorded: 10/07/2014Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
08/28/2014
Assignee:
SCHÖNBRUNNER STRASSE 7
WIEN, AUSTRIA A-1040
Correspondent:
KPPB LLP
2400 E. KATELLA AVENUE
SUITE 1050
ANAHEIM, CA 92806
Assignment: 2
Reel/Frame:
047648/0566Recorded: 09/14/2018Pages: 29
Conveyance:
MERGER (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
09/21/2017
Assignee:
SCHOENBRUNNERSTRASSEE 7
WIEN, AUSTRIA 1040
Correspondent:
JEREMY SPIER / EVERSHEDS SUTHERLAND
999 PEACHTREE STREET NE
SUITE 2300
ATLANTA, GA 30309

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