Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/27/2015
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Application #:
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14488039
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Filing Dt:
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09/16/2014
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Inventors:
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Peng Zhang, Nan Zhuang, Yuhua Yang
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Title:
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Method and System for Reducing Redundant Logic in an Integrated Circuit
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2655 SEELY AVENUE |
SAN JOSE, CALIFORNIA 95134 |
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DICKSTEIN SHAPIRO LLP |
2049 CENTURY PARK EAST |
SUITE 700 |
LOS ANGELES, CA 90067 |
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