Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/01/2016
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Application #:
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12847647
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Filing Dt:
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07/30/2010
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Publication #:
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Pub Dt:
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02/02/2012
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Inventors:
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Yi-Tzu Chen, Bin-Hau Lo, Tsai-Hsin Lai, Hau-Tai Shieh, Pey-Huey Chen
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Title:
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Split Bit Line Architecture Circuits and Methods for Memory Devices
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO. 8, LI-HSIN RD. 6 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 R.O.C. |
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| SLATER & MATSIL, L.L.P. |
| 17950 PRESTON ROAD |
| SUITE 1000 |
| DALLAS, TX 75252 |
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