Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/05/2016
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Application #:
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14024925
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Filing Dt:
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09/12/2013
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Publication #:
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Pub Dt:
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01/09/2014
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Inventors:
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Jaw-Juinn HORNG, Chia-Lin Yu, Chung-Hui Chen, Der-Chyang Yeh, Yung-Chow Peng
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Title:
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THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 8105 RASOR BLVD. STE 210 |
| PLANO, TEXAS 75024 |
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| DO KIM |
| 8105 RASOR BLVD |
| PLANO, TX 75024 |
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