Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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06/13/2017
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Application #:
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15073583
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Filing Dt:
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03/17/2016
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Inventors:
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Venkatesan Rajappan, Sunil Sharma, Mohan Tandyala
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Title:
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EARLY GLOBAL SET/RESET SIGNAL DETERMINATION FOR PROGRAMMABLE LOGIC DEVICES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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111 SW 5TH AVENUE, 7TH FLOOR |
PORTLAND, OREGON 97204 |
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HAYNES AND BOONE, LLP |
2323 VICTORY AVENUE, SUITE 700 |
DALLAS, TX 75219 |
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Assignment:
2
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SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
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520 MADISON AVENUE |
NEW YORK, NEW YORK 10022 |
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MICHAEL GALLAGHER |
PROSKAUER ROSE LLP |
ELEVEN TIMES SQUARE |
NEW YORK, NY 10036-8299 |
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Assignment:
3
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SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
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1700 LINCOLN STREET, 3RD FLOOR |
MAC C7300-033 |
DENVER, COLORADO 80203-4500 |
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BETTY G. SMITH, SENIOR PARALEGAL |
MCGUIREWOODS LLP, 201 N. TRYON ST. |
SUITE 3000 |
CHARLOTTE, NC 28202 |
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