Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/07/2017
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Application #:
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14984020
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Filing Dt:
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12/30/2015
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Publication #:
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Pub Dt:
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10/13/2016
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Inventor:
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Senthilkumar Jayapal
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Title:
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Standby Mode State Retention Logic Circuits
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO.1 FUSIONOPOLIS WALK, #3-01 SOLARIS |
| SINGAPORE, SINGAPORE 138628 |
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| LAW OFFICE OF ZHENG JIN |
| P.O.BOX 731450 |
| SAN JOSE, CA 95173 |
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