Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/09/2018
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Application #:
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15019504
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Filing Dt:
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02/09/2016
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Inventors:
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Puneet ARORA, Steven Lee GREGOR, Norman Robert CARD, Navneet KAUSHIK
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Title:
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METHOD AND APPARATUS FOR TESTING ERROR CORRECTION CODE (ECC) LOGIC AND PHYSICAL MEMORY ONBOARD A MANUFACTURED INTEGRATED CIRCUIT (IC)
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2655 SEELY AVENUE |
| BUILDING 5 |
| SAN JOSE, CALIFORNIA 95134 |
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| CADENCE DESIGN SYSTEMS, INC. - KENYON |
| C/O KENYON & KENYON LLP |
| 1801 PAGE MILL ROAD, SUITE 210 |
| PALO ALTO, CA 94304-1216 |
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