Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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12/13/2011
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Application #:
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12724026
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Filing Dt:
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03/15/2010
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Inventors:
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Takanobu Nakashima, Tatsuhisa Matsunaga, Hidehiro Yanagawa
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Title:
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DUAL LOADING PORT SEMICONDUCTOR PROCESSING EQUIPMENT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3-4, KANDAKAJI-CHO, CHIYODA-KU |
| TOKYO, JAPAN 1010045 |
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| MORGAN, LEWIS & BOCKIUS LLP |
| 1400 PAGE MILL ROAD |
| PALO ALTO, CA 94304 |
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