Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
09/23/2003
|
Application #:
|
10106103
|
Filing Dt:
|
03/27/2002
|
|
Publication #:
|
|
Pub Dt:
|
10/24/2002
| | | | |
|
Inventors:
|
Yoshio Kaneko, Yoshihisa Tamura
|
|
Title:
|
SEMICONDUCTOR CIRCUIT DEVICE HAVING GATE ARRAY AREA AND METHOD OF MAKING THEREOF
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 1-1-1 SHIBAURA, MINATO-KU |
| TOKYO, JAPAN |
|
|
|
|
| FINNEGAN, HENDERSON, FARABOW, ET AL. |
| ERNEST F. CHAPMAN |
| 1300 I STREET, NW |
| WASHINGTON, DC 20005-3315 |
|
|
Search Results as of:
05/07/2024 08:26 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
