Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10157269
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Filing Dt:
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05/28/2002
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Publication #:
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Pub Dt:
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12/04/2003
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Inventor:
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Manish Singh
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Title:
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Method and apparatus for characterizing timing-sensitive digital logic circuits
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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901 SAN ANTONIO ROAD |
PALO ALTO, CALIFORNIA 94303 |
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THELEN REID & PRIEST LLP |
DAVID B. RITCHIE |
P.O. BOX 640640 |
SAN JOSE, CA 95164-0640 |
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