Patent Assignment Abstract of Title
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Total Assignments:
4
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10167039
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Filing Dt:
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06/11/2002
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Publication #:
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Pub Dt:
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12/11/2003
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Inventors:
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Sergei Bakarian, Julie Segal
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Title:
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METHOD FOR AVOIDING FALSE FAILURES ATTRIBUTABLE TO DUMMY INTERCONNECTS DURING DEFECT ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2033 GATEWAY PLACE |
| SAN JOSE, CALIFORNIA 95110 |
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| HPL TECHNOLOGIES, INC. |
| VICTOR H. OKUMOTO |
| 2033 GATEWAY PLACE |
| SAN JOSE, CA 95110 |
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Assignment:
2
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| 3003 TASMAN DRIVE |
| SANTA CLARA, CALIFORNIA 95054-1191 |
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| ANTOINETTE F. KONSKI |
| C/O BINGHAM MCCUTCHEN LLP |
| THREE EMBARCADERO CENTER, SUITE 1800 |
| SAN FRANCISCO, CA 94111-4067 |
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Assignment:
3
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| 2033 GATEWAY PLACE STE 400 |
| SAN JOSE, CALIFORNIA 95110 |
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| SILICON VALLEY BANK |
| LOAN COLLATERAL HF154 |
| 3003 TASMAN DRIVE |
| SANTA CLARA, CA 95054 |
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Assignment:
4
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 700 E. MIDDLEFIELD RD. |
| MOUNTAIN VIEW, CALIFORNIA 94043 |
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| TED W. CHAN |
| SYNOPSYS, INC. |
| 700 E. MIDDLEFIELD RD. |
| MOUNTAIN VIEW, CA 94043 |
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