Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10637749
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Filing Dt:
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08/08/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Inventors:
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Dieter Spaderna, Dale Wong
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Title:
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Via programmable gate array interconnect architecture
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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6 RESULTS WAY |
CUPERTINO, CALIFORNIA 95014 |
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RITTER, LANG & KAPLAN LLP |
GARY T. AKA |
12930 SARATOGA AVE., SUITE D1 |
SARATOGA, CA 95070 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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6 RESULTS WAY |
CUPERTINO, CALIFORNIA 95014 |
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EMIL CHANG |
874 JASMINE DRIVE |
SUNNYVALE, CA 94086 |
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09/26/2024 03:15 PM
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