Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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07/10/2007
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Application #:
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10449669
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Filing Dt:
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05/30/2003
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Publication #:
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Pub Dt:
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12/02/2004
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Inventors:
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Albert Zihui Wang, Rouying Zhan
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Title:
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PARAMETER CHECKING METHOD FOR ON-CHIP ESD PROTECTION CIRCUIT PHYSICAL DESIGN LAYOUT VERIFICATION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 10 WEST 33RD STREET |
| CHICAGO, ILLINOIS 60616 |
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| PAULEY PETERSON KINNE & ERICKSON |
| ROLAND W. NORRIS |
| 2800 WEST HIGGINS ROAD |
| SUITE 365 |
| HOFFMAN ESTATES, IL 60195 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 56 BOULDER CREEK WAY |
| IRVINE, CALIFORNIA 92602 |
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| ALBERT WANG |
| 56 BOULDER CREEK WAY |
| IRVINE, CA 92602 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1128 FUSHAN AVE., |
| XIAOLAN ECONOMY AND TECHNOLOGY DEVELOPMENT DISTRICT |
| NANCHANG, CHINA |
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| ALBERT WANG |
| 56 BOULDER CREEK WAY |
| IRVINE, CA 92602 |
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