Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10863327
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Filing Dt:
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06/09/2004
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Publication #:
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Pub Dt:
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01/06/2005
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Inventors:
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Shouzou Hirano, Kenji Shimazaki, Hiroyuki Tsujikawa
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Title:
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Substrate noise analyzing method for semiconductor integrated circuit, semiconductor integrated circuit, and substrate noise analyzing device for semiconductor integrated circuit
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006, OAZA KADOMA |
| KADOMA-SHI, OSAKA, JAPAN 571-8501 |
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| MCDERMOTT WILL & EMERY LLP |
| MICHAEL E. FOGARTY |
| 600 13TH STREET, NW |
| WASHINGTON, DC 2005-3096 |
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