Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10616850
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Filing Dt:
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07/10/2003
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Publication #:
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Pub Dt:
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01/13/2005
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Inventors:
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Sang Hoo Dhong, Hwa-Joon Oh, Joel Abraham Silberman, Naoka Yano
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Title:
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INTEGRATED LOGIC AND LATCH DESIGN WITH CLOCK GATING AT STATIC INPUT SIGNALS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1 SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, 105-8001, JAPAN |
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| KABUSHIKI KAISHA TOSHIBA |
| ROBERT M. CARWELL |
| 1-1 SHIBAURA 1-CHOME |
| MINATO-KU, TOKYO, 105-8001, JAPAN |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
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| IBM CORPORATION |
| ROBERT M CARWELL |
| INTELLECTUAL PROPERTY LAW |
| 11400 BURNET ROAD |
| AUSTIN, TX 78758 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 9775 TOLEDO WAY |
| IRVINE, CALIFORNIA 92618 |
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| TOSHIBA AMERICA ELECTRONIC COMPONENTS, |
| INC |
| MASSAKI NOMI |
| 9775 TOLEDO WAY |
| IRVINE, CA 92618 |
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