Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10671771
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Filing Dt:
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09/29/2003
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Publication #:
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Pub Dt:
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03/31/2005
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Inventors:
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S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
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Title:
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Method for fabricating wafer-level chip scale packages
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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CEDAR HOUSE, 41 CEDAR AVENUE |
HAMILTON, BERMUDA HM 12 |
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NO. 1, R&D RD. 1 |
SCIENCE-BASED INDUSTRIAL PARK |
HSINCHU, TAIWAN R.O.C. |
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BIRCH, STEWART, KOLASCH & BIRCH, LLP |
JOE MCKINNEY MUNCY |
P.O. BOX 747 |
FALLS CHURCH, VA 22040-0747 |
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