Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/31/2009
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Application #:
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11019365
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Filing Dt:
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12/23/2004
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Publication #:
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Pub Dt:
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05/19/2005
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Inventor:
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Toshiyuki Shibuya
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Title:
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METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT ENABLING THE YIELD OF INTERGRATED CIRCUIT TO BE IMPROVED BY CONSIDERING RANDOM ERRORS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1-1, KAMIKODANAKA 4-CHOME |
NAKAHARA-KU, KAWASAKI-SHI |
KANAGAWA, 211-8588, JAPAN |
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STAAS & HALSEY LLP |
ATTENTION: DAVID M. PITCHER |
1201 NEW YORK AVE., N.W. |
SUITE 700 |
WASHINGTON, DC 20005 |
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