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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
11076939
Filing Dt:
03/11/2005
Publication #:
Pub Dt:
09/15/2005
Inventors:
Kiyohito Mukai, Mitsumi Itou, Ritsuko Ozoe, Tatsuo Ohashi, Hiroyuki Tsujikawa
Title:
Layout data verification method, mask pattern verification method and circuit operation verification method
Assignment: 1
Reel/Frame:
016963/0646Recorded: 09/09/2005Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
12/03/2004
Exec Dt:
12/03/2004
Exec Dt:
12/03/2004
Exec Dt:
12/03/2004
Exec Dt:
12/03/2004
Assignee:
1006, OAZA KADOMA
KADOMA-SHI, OSAKA 571-8501, JAPAN
Correspondent:
MCDERMOTT WILL & EMERY LLP
600 13TH STREET, N.W.
WASHINGTON, DC 20005-3096

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