Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
Total Assignments:
2
|
Patent #:
|
|
Issue Dt:
|
11/20/2007
|
Application #:
|
10898273
|
Filing Dt:
|
07/23/2004
|
Publication #:
|
|
Pub Dt:
|
01/26/2006
| | | | |
Inventors:
|
Zhong Dong, Chuck Jang, Ching-Hwa Chen, Chia-Shun Hsiao
|
Title:
|
METHOD FOR SIMULTANEOUSLY FABRICATING ONO-TYPE MEMORY CELL, AND GATE DIELECTRICS FOR ASSOCIATED HIGH VOLTAGE WRITE TRANSISTORS AND GATE DIELECTRICS FOR LOW VOLTAGE LOGIC TRANSISTORS BY USING ISSG
|
|
Assignment:
1
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
3F, NO. 19, LI-HSING ROAD, HSIN-CHU |
SCIENCE-BASED INDUSTRIAL PARK |
HSING-CHU, TAIWAN |
|
|
|
MACPHERSON, KWOK CHEN & HEID LLP |
GIDEON GIMLAN |
1762 TECHNOLOGY DRIVE, SUITE 226 |
SAN JOSE, CA 95110 |
|
|
Assignment:
2
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
3F, NO. 19, LI-HSING ROAD, HSIN-CHU |
SCIENCE BASED INDUSTRIAL PARK |
HSING-CHU, TAIWAN |
|
|
|
MACPHERSON, KWOK CHEN & HEID LLP |
GIDEON GIMLAN |
1762 TECHNOLOGY DRIVE, SUITE 226 |
SAN JOSE, CA 95110 |
|
|
Search Results as of:
05/11/2024 09:24 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|