Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
2
|
|
Patent #:
|
|
Issue Dt:
|
01/30/2007
|
Application #:
|
10711536
|
Filing Dt:
|
09/24/2004
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2006
| | | | |
|
Inventors:
|
Min-Chih Hsuan, Paul Chen, Hermen Liu, Kun-Chih Wang, Kai-Kuang Ho
|
|
Title:
|
METHOD FOR MANUFACTURING WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| NO. 3, LI-HSIN RD. II, SCIENCE-BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN |
|
|
|
|
| JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE |
| 7 FLOOR-1, NO. 100 |
| ROOSEVELT ROAD, SECTION 2 |
| TAIPEI, TAIWAN 100 |
|
|
|
Assignment:
2
|
|
|
|
|
|
|
RECORD TO CORRECT THE THIRD INVENTOR'S NAME ON THE PATENT ASSIGNMENT RECORDATION COVER SHEET PREVIOUSLY RECORDED AT REEL/FRAME 015168/0778
|
|
|
|
|
|
|
|
|
| NO. 3, LI-HSIN RD. II |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSINCHU, TAIWAN R.O.C. |
|
|
|
|
| JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE |
| 7F.-1, NO. 100, ROOSEVELT RD. |
| SEC. 2, TAIPEI 100, TAIWAN, R.O.C. |
|
|
Search Results as of:
09/20/2024 06:30 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
