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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
NONE
Issue Dt:
Application #:
11066712
Filing Dt:
02/24/2005
Publication #:
Pub Dt:
08/24/2006
Inventor:
Shannon Vance Morton
Title:
Logic cell layout architecture with shared boundary
Assignment: 1
Reel/Frame:
016248/0690Recorded: 05/17/2005Pages: 2
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/27/2005
Assignee:
2520 THE QUANDRANT
AZTEC WEST, ALMONDSBURY
BRISTOL BS32 4AQ, UNITED KINGDOM
Correspondent:
MCDERMOTT WILL & EMERY LLP
18191 VON KARMAN AVE., SUITE 400
IRVINE, CA 92612-7107
Assignment: 2
Reel/Frame:
021510/0707Recorded: 09/10/2008Pages: 19
Conveyance:
SECURITY AGREEMENT
Assignor:
Exec Dt:
08/29/2008
Assignee:
6 RUE PHILLIPPE II
L-2340 LUXEMBOURG, LUXEMBOURG
Correspondent:
GUNDERSON DETTMER
610 LINCOLN STREET
WALTHAM, MA 02451

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