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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
NONE
Issue Dt:
Application #:
11525428
Filing Dt:
09/22/2006
Publication #:
Pub Dt:
01/25/2007
Inventors:
Chintamani Palsule, Jay Meyer, John H. Stanback, Jeremy A. Theil, Kirk A. Lindahl et al
Title:
Method for fabricating low leakage interconnect layers in integrated circuits
Assignment: 1
Reel/Frame:
023921/0794Recorded: 02/09/2010Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
11/22/2006
Assignee:
UNIT LEVEL 13 MAIN OFFICER TOWER
FINANCIAL PARK LABUAN JALAN, MERDEKA
LABUAN, MALAYSIA 87000
Correspondent:
KENNETH N. NIGON
1235 WESTLAKES DRIVE, SUITE 301
RATNERPRESTIA
BERWYN, PA 19312
Assignment: 2
Reel/Frame:
023159/0424Recorded: 08/27/2009Pages: 49
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
10/03/2008
Assignee:
WALKER HOUSE, 87 MARY STREET
GEORGE TOWN
GRAND CAYMAN, CAYMAN ISLANDS KY1-9002
Correspondent:
KENNETH N. NIGON
1235 WESTLAKES DRIVE, SUITE 301
RATNERPRESTIA
BERWYN, PA 19312

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