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Patent Assignment Abstract of Title
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Total Assignments: 3
Patent #:
Issue Dt:
06/23/2009
Application #:
11506759
Filing Dt:
08/18/2006
Publication #:
Pub Dt:
03/22/2007
Inventors:
Michel Briet, Arnaud Verdant
Title:
LOGIC CELL WITH TWO ISOLATED REDUNDANT OUTPUTS, AND CORRESPONDING INTEGRATED CIRCUIT
Assignment: 1
Reel/Frame:
023234/0513Recorded: 09/16/2009Pages: 14
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/01/2006
Assignee:
ROUTE DES ARSENAUX 41
CASE POSTALE 80
FRIBOURG, SWITZERLAND 1705
Correspondent:
JONES DAY
222 EAST 41ST STREET
NEW YORK, NY 10017
Assignment: 2
Reel/Frame:
018659/0723Recorded: 12/04/2006Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
11/10/2006
Exec Dt:
11/07/2006
Assignee:
LA CHANTRERIE, BP 70602
NANTES CEDEX 3, FRANCE 44306
Correspondent:
DAVID D. BRUSH
WESTMAN, CHAPLIN & KELLY, P.A.
SUITE 1400
900 SECOND AVENUE SOUTH
MINNEAPOLIS, MN 55402
Assignment: 3
Reel/Frame:
024023/0282Recorded: 03/04/2010Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
03/03/2010
Assignee:
ZONE INDUSTRIELLE
AVENUE OLIVIER PERROY
ROUSSET CEDEX, FRANCE 13106
Correspondent:
JONES DAY
222 EAST 41ST STREET
NEW YORK, NY 10017

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