Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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01/13/2009
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Application #:
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11342125
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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07/26/2007
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Inventors:
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Yu-Chin Hsu, Furshing Tsai, Wori-Tzy Jong
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Title:
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DEBUGGING SYSTEM FOR GATE LEVEL IC DESIGNS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2025 GATEWAY PLACE, SUITE 480 |
| SAN JOSE, CALIFORNIA 95110 |
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| PENNY STOCKWELL |
| 16100 N.W. CORNELL ROAD, SUITE 220 |
| BEAVERTON, OR 97006 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2025 GATEWAY PLACE, SUITE 400 |
| SAN JOSE, CALIFORNIA 95110 |
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| PENNY STOCKWELL |
| 16100 NW CORNELL ROAD, SUITE 220 |
| BEAVERTON, OR 97006 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 700 E. MIDDLEFIELD RD. |
| MOUNTAIN VIEW, CALIFORNIA 94043 |
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| KILPATRICK TOWNSEND & STOCKTON LLP |
| TWO EMBARCADERO CENTER, 8TH FLOOR |
| SAN FRANCISCO, CA 94111-3834 |
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