Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/08/2010
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Application #:
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11683759
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Filing Dt:
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03/08/2007
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Publication #:
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Pub Dt:
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09/27/2007
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Inventors:
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Kenichi Anzou, Chikako Tokunaga, Tetsu Hasegawa
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Title:
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SEMICONDUCTOR INTERGRATED CIRCUIT HAVING BUILT-N SELF TEST CIRCUIT OF LOGIC CIRCUIT AND EMBEDDED DEVICE, AND DESIGN APPARATUS THEROF
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1-1, SHIBAURA 1-CHOME |
MINATO-KU, TOKYO, JAPAN 105-8001 |
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AMIN, TUROCY & CALVIN, LLP |
24TH FLOOR, NATIONAL CITY CENTER |
1900 EAST NINTH STREET |
CLEVELAND, OH 44114 |
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