Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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09/21/2010
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Application #:
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11777761
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Filing Dt:
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07/13/2007
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Publication #:
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Pub Dt:
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01/15/2009
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Inventors:
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Louis Chaochiuan Liu, Hsing-Chien Huang, Ssu-Chia Chang
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Title:
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METHOD FOR REDUCING TIMING LIBRARIES FOR INTRA-DIE MODEL IN STATISTICAL STATIC TIMING ANALYSIS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NO.8 LI-HSIN ROAD 6, SCIENCE BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
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| HOWARD CHEN, ESQ. K&L GATES, LLP |
| 55 SECOND STREET |
| SUITE 1700 |
| SAN FRANCISCO, CA 94105 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 019557 FRAME 0784. ASSIGNOR(S) HEREBY CONFIRMS THE RECORDED ASSIGNMENT AND AGREEMENT CORRECTLY LISTS THE ASSIGNEE AS "TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.".
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| NO. 8, LI-HSIN ROAD 6, SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
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| JONG HO LEE, K&L GATES LLP |
| FOUR EMBARCADERO CENTER, SUITE 1200 |
| SAN FRANCISCO, CA 94111 |
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