Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/18/2010
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Application #:
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11832021
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Filing Dt:
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08/01/2007
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Publication #:
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Pub Dt:
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02/05/2009
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Inventors:
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Keerthinarayan P. Heragu, Padattil K. Nisha
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Title:
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GLITCH REDUCED DELAY LOCK LOOP CIRCUITS AND METHODS FOR USING SUCH
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 12500 TI BOULEVARD |
| DALLAS, TEXAS 75243-4136 |
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| ALAN STEWART |
| P.O. BOX 655474 |
| M/S 3999 |
| DALLAS, TX 75265 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 12500 TI BOULEVARD |
| DALLAS, TEXAS 75243-4136 |
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| ALAN STEWART |
| M/S 3999 |
| P.O. BOX 655474 |
| DALLAS, TX 75265 |
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