Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/01/2011
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Application #:
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12165933
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Filing Dt:
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07/01/2008
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Publication #:
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Pub Dt:
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01/07/2010
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Inventors:
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Peter J. Hopper, William French, Ann Gabrys
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Title:
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ISOLATION TECHNIQUE ALLOWING BOTH VERY HIGH AND LOW VOLTAGE CIRCUITS TO BE FABRICATED ON THE SAME CHIP
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2900 SEMICONDUCTOR DRIVE |
SANTA CLARA, CALIFORNIA 95051 |
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STALLMAN & POLLOCK LLP |
ATTN: MICHAEL J. POLLOCK |
353 SACRAMENTO STREET, SUITE 2200 |
SAN FRANCISCO, CA 94111 |
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