Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/17/2011
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Application #:
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12627743
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Filing Dt:
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11/30/2009
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Publication #:
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Pub Dt:
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03/25/2010
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Inventors:
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Saptharishi Sriram, Matt Willis
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Title:
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METHODS OF FABRICATING TRANSISTORS HAVING BURIED P-TYPE LAYERS COUPLED TO THE GATE
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Assignment:
1
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CONFIRMATORY LICENSE (SEE DOCUMENT FOR DETAILS).
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875 NORTH RANDOLPH |
OFFICE OF NAVAL RESEARCH |
ARLINGTON, VIRGINIA USA 22203-1995 |
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CAROL PETROSKY |
OFFICE OF NAVAL RESEARCH |
OFFICE OF COUNSEL |
875 NORTH RANDOLPH STREET |
ARLINGTON, VA 22203-1995 |
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Assignment:
2
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SECURITY INTEREST (SEE DOCUMENT FOR DETAILS).
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214 N. TRYON STREET, 27TH FLOOR |
MAIL CODE CN-NC-H27A |
CHARLOTTE, NORTH CAROLINA 28202 |
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NIKOLAI DOKKEDAHL |
1285 AVENUE OF THE AMERICAS |
PAUL WEISS RIFKIND WHARTON &GARRISON LLP |
NEW YORK, NY 10019-6064 |
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