Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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08/16/2011
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Application #:
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12597106
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Filing Dt:
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10/22/2009
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Publication #:
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Pub Dt:
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04/15/2010
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Inventors:
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Xiaoqing Wen, Kohei Miyase, Seiji Kajihara
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Title:
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TEST PATTERN GENERATION METHOD FOR AVOIDING FALSE TESTING IN TWO-PATTERN TESTING FOR SEMICONDUCTOR INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1-1, SENSUI-CHO, TOBATA-KU, |
KITAKYUSHU-SHI, FUKUOKA, JAPAN 804-8550 |
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WESTERMAN, HATTORI, DANIELS & ADRIAN LLP |
1250 CONNECTICUT AVENUE NW, |
SUITE 700 |
WASHINGTON,, DC 20036 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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11-13 MINAMI-AOYAMA 2-CHOME |
MINTO-KU, TOKYO, JAPAN 107-0062 |
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RANKIN, HILL & CLARK |
23755 LORAIN ROAD |
SUITE 200 |
NORTH OLMSTED, OH 44070 |
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