Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/17/2015
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Application #:
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13550008
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Filing Dt:
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07/16/2012
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Publication #:
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Pub Dt:
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11/08/2012
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Inventors:
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Michiko INOUE, Tomokazu YONEDA, Yasuo SATO
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Title:
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TEST PATTERN GENERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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8916-5, TAKAYAMA-CHO, IKOMA-SHI |
NARA, JAPAN 630-0192 |
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1-1, SENSUI-CHO, TOBATA-KU |
KITAKYUSHU-SHI |
FUKUOKA, JAPAN 804-8550 |
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STUDEBAKER & BRACKETT PC |
12700 SUNRISE VALLEY DRIVE |
SUITE 102 |
RESTON, VA 20191 |
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