Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/05/2013
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Application #:
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13587733
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Filing Dt:
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08/16/2012
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Publication #:
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Pub Dt:
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03/14/2013
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Inventors:
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Marc Heyns, Cedric Huyghebaert, Anne S. Verhulst, Daniele Leonelli, Rita Rooyackers et al
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Title:
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TUNNEL TRANSISTOR, LOGICAL GATE INCLUDING THE TRANSISTOR, STATIC RANDOM-ACCESS MEMORY USING THE LOGICAL GATE AND METHOD FOR MAKING SUCH A TUNNEL TRANSISTOR
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| KAPELDREEF 75 |
| LEUVEN, BELGIUM 3001 |
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| WAAISTRAAT 6 - BOX 5105 |
| LEUVEN, BELGIUM 3000 |
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| ROSE M. THIESSEN |
| 2040 MAIN STREET, 14TH FLOOR |
| IRVINE, CA 92614 |
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