Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/10/2014
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Application #:
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13547520
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Filing Dt:
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07/12/2012
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Publication #:
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Pub Dt:
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06/06/2013
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Inventors:
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Tsung-Yi Ho, Sheng-Jhih Jiang, Chan-Liang Wu
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Title:
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METHOD OF RESISTOR MATCHING IN ANALOG INTEGRATED CIRCUIT LAYOUT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NO. 1, UNIVERSITY ROAD |
TAINAN, TAIWAN 701 |
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NO.26, ZILIAN RD., XINSHI DIST. |
TAINAN CITY, TAIWAN |
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STOUT, UXA, BUYAN & MULLINS LLP |
4 VENTURE, SUITE 300 |
IRVINE, CA 92618 |
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