Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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NONE
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Issue Dt:
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Application #:
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14033842
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Filing Dt:
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09/23/2013
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Publication #:
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Pub Dt:
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03/27/2014
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Inventors:
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Masayuki HASHITANI, Hirofumi HARADA
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Title:
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Semiconductor integrated circuit device comprising an enhancement type NMOS having a positive threshold voltage and an depression type NMOS having a negative threshold voltage, wherein a P-type impurity layer provided under the N-type channel impurity region.
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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8, NAKASE 1-CHOME, MIHAMA-KU |
CHIBA-SHI, CHIBA, JAPAN 261-8507 |
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BRUCE L. ADAMS, ESQ. |
ADAMS & WILKS |
17 BATTERY PLACE - SUITE 1343 |
NEW YORK, NY 10004 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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8, NAKASE 1-CHOME, MIHAMA-KU |
CHIBA-SHI, CHIBA, JAPAN 261-8507 |
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ADAMS & WILKS |
17 BATTERY PLACE |
SUITE 1343 |
NEW YORK, NY 10004 |
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