Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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11/20/2018
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Application #:
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15247185
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Filing Dt:
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08/25/2016
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Publication #:
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Pub Dt:
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03/02/2017
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Inventors:
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Hossein Moradian, Jeong A LEE
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Title:
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Fault localization and error correction method for self-checking binary signed-digit adder and digital logic circuit for the method
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 309, PILMUN-DAERO, DONG-GU |
| GWANGJU, KOREA, REPUBLIC OF 61452 |
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| THE PL LAW GROUP, PLLC |
| 5875 TRINITY PARKWAY |
| SUITE 110 |
| CENTERVILLE, VA 20120 |
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