Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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15201402
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Filing Dt:
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07/02/2016
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Publication #:
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Pub Dt:
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01/04/2018
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Inventors:
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Gwang-Hyun Gho, Matthew Hayes
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Title:
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BIT-ERROR RATE FALSE POSITIVE DETECTION SYSTEM AND METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2200 MISSION COLLEGE BOULEVARD |
SANTA CLARA, CALIFORNIA 95054 |
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INTEL IP CORPORATION / INTEL CORPORATION |
900 2ND AVENUE SOUTH, SUITE 600 |
MINNEAPOLIS, MN 55402 |
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09/24/2024 09:39 AM
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