Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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04/09/2019
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Application #:
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15788277
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Filing Dt:
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10/19/2017
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Publication #:
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Pub Dt:
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04/26/2018
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Inventor:
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Nihar Mohanty
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Title:
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Method of Reducing Overlay Error in Via to Grid Patterning
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 3-1 AKASAKA 5-CHOME |
| AKASAKA BIZ TOWER |
| MINATO-KU, TOKYO, JAPAN 107-6325 |
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| TOKYO ELECTRON U.S. HOLDINGS, INC. |
| 2400 GROVE BLVD. |
| AUSTIN, TX 78741 |
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