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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
11257560
Issue Dt:
02/22/2022
Application #:
15717721
Filing Dt:
09/27/2017
Publication #:
20190096503
Pub Dt:
03/28/2019
Inventors:
Fei SU, Sreejit CHAKRAVARTY, Puneet GUPTA, Terrence Huat Hin TAN, Anubhav SINHA et al
Title:
DESIGN FOR TEST ARCHITECTURE FOR DIE TO DIE INTERCONNECT FOR THREE DIMENSIONAL INTEGRATED CIRCUITS
Assignment: 1
Reel/Frame:
044519/0570Recorded: 01/02/2018Pages: 22
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
CHAKRAVARTY, SREEJIT
Exec Dt:
10/26/2017
SU, FEI
Exec Dt:
10/30/2017
GUPTA, PUNEET
Exec Dt:
10/23/2017
LIM, WEI MING
Exec Dt:
10/24/2017
TAN, TERRENCE HUAT HIN
Exec Dt:
10/28/2017
SANGHANI, AMIT
Exec Dt:
10/26/2017
SINHA, ANUBHAV
Exec Dt:
11/03/2017
BADANA, SUDHEER V
Exec Dt:
11/18/2017
KANDULA, RAKESH
Exec Dt:
11/07/2017
B. S., ADITHYA
Exec Dt:
10/25/2017
Assignee:
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD
SANTA CLARA, CALIFORNIA 95054
Correspondent:
JONATHAN S. MILLER
99 ALMADEN BOULEVARD | SUITE 710
SAN JOSE, CA 95113

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