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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
10951212
Issue Dt:
03/16/2021
Application #:
16270323
Filing Dt:
02/07/2019
Publication #:
20190190520
Pub Dt:
06/20/2019
Inventors:
Gopal Raghavan, Vidura Manu Wijayasekara, David Cureton Baker, Chao Xu et al
Title:
SELF-TIMED PROCESSORS IMPLEMENTED WITH MULTI-RAIL NULL CONVENTION LOGIC AND UNATE GATES
Assignment: 1
Reel/Frame:
048271/0649Recorded: 02/07/2019Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
XU, CHAO
Exec Dt:
04/05/2018
RAGHAVAN, GOPAL
Exec Dt:
04/06/2018
MELTON, BEN WILEY
Exec Dt:
04/09/2018
WIJAYASEKARA, VIDURA MANU
Exec Dt:
04/06/2018
COPE, BRYAN GARNETT
Exec Dt:
04/06/2018
BAKER, DAVID CURETON
Exec Dt:
04/05/2018
HAVLICEK, JOHN WHITAKER
Exec Dt:
04/05/2018
Assignee:
ETA COMPUTE, INC.
310 N. WESTLAKE BLVD., SUITE 110
WESTLAKE VILLAGE, CALIFORNIA 91362
Correspondent:
SOCAL IP LAW GROUP LLP
310 N. WESTLAKE BLVD., SUITE 120
WESTLAKE VILLAGE, CA 91362
Assignment: 2
Reel/Frame:
066232/0020Recorded: 01/24/2024Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
ETA COMPUTE, INC.
Exec Dt:
11/27/2023
Assignee:
SAMSUNG ELECTRONICS CO., LTD.
1-1 SAMSUNGJEONJA-RO
HWASEONG-SI, GYEONGGI-DO, KOREA, REPUBLIC OF 18448
Correspondent:
JOHN A. CASTELLANO
12950 WORLDGATE DR., SUITE 750
HERNDON, VA 20170

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