Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/09/2021
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Application #:
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15922682
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Filing Dt:
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03/15/2018
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Publication #:
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Pub Dt:
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09/19/2019
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Inventors:
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Che-Liang Chung, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
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Title:
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FORMING GATE LINE-END OF SEMICONDUCTOR STRUCTURES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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8, LI-HSIN RD. 6, HSINCHU SCIENCE PARK |
HSINCHU, TAIWAN 300-78 |
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SEED IP LAW GROUP LLP |
701 5TH AVENUE |
STE 5400 |
SEATTLE, WA 98104 |
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09/20/2024 06:55 AM
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