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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
NONE
Issue Dt:
Application #:
17031822
Filing Dt:
09/24/2020
Publication #:
Pub Dt:
01/14/2021
Inventors:
Swadesh Choudhary, Mahesh Wagh, Debendra Das Sharma
Title:
Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Packets for Computer Buses
Assignment: 1
Reel/Frame:
053879/0315Recorded: 09/24/2020Pages: 5
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
09/13/2020
Exec Dt:
09/01/2020
Exec Dt:
09/23/2020
Assignee:
2200 MISSION COLLEGE BLVD.
SANTA CLARA, CALIFORNIA 95054
Correspondent:
ALLIANCE IP LLC
20 E. THOMAS ROAD, SUITE 2200
PHOENIX, AZ 85012

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