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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
11360667
Issue Dt:
06/14/2022
Application #:
17012501
Filing Dt:
09/04/2020
Publication #:
20210072894
Pub Dt:
03/11/2021
Inventors:
Nitin CHAWLA, Anuj GROVER, Surinder Pal SINGH, Giuseppe DESOLI, Thomas BOESCH et al
Title:
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
Assignment: 1
Reel/Frame:
053722/0521Recorded: 09/09/2020Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
CHAWLA, NITIN
Exec Dt:
01/08/2020
GROVER, ANUJ
Exec Dt:
01/07/2020
BOESCH, THOMAS
Exec Dt:
01/08/2020
SINGH, SURINDER PAL
Exec Dt:
01/08/2020
AYODHYAWASI, MANUJ
Exec Dt:
01/08/2020
Assignee:
STMICROELECTRONICS INTERNATIONAL N.V.
CHEMIN DU CHAMP-DES-FILLES 39
PLAN-LES-OUATES
GENEVA, SWITZERLAND 1228
Correspondent:
SEED IP LAW GROUP LLP
701 5TH AVE, SUITE 5400
SEATTLE, WA 98104
Assignment: 2
Reel/Frame:
053722/0540Recorded: 09/09/2020Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
DESOLI, GIUSEPPE
Exec Dt:
09/09/2020
Assignee:
STMICROELECTRONICS S.R.L.
VIA C. OLIVETTI, 2
AGRATE BRIANZA, ITALY 20864
Correspondent:
SEED IP LAW GROUP LLP
701 5TH AVE, SUITE 5400
SEATTLE, WA 98104

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